Hybrid approach for performance estimation; embedded tool for analog design automation systems

A novel approach for performance estimation is described which gives the designer access to the design space boundaries of a circuit topology so that the tradeoff analysis of competing performances can be evaluated by optimum design points and Pareto curves with an acceptable execution time and transistor-level accuracy can be obtained. Recently, there is a strong emphasis on numerical techniques for performance estimation models however neither of them satisfies the following three significant issues; accuracy, time-consumption and topology-independent modeling. This new approach allows using different performance estimation methods together in order to speed up the overall design automation system with an acceptable time and accuracy for any given topology

A novel equivalent circuit model for split ring resonator with an application of low phase noise reference oscillator

This paper presents physical lumped element models for the structures employing a split-ring resonator (SRR) coupled with a pair of microstrip antennas. The results of 3D EM simulations, circuit simulations and measurement results are provided. For experimental verification, a resonator device was fabricated on an FR4 epoxy glass substrate. Mismatch between the values of resonant frequency that are predicted by the models and that are measured is less than 3%. As a benchmarking case for the proposed model, a reference oscillator was designed and implemented. A phase noise of −139.51 dBc/Hz at 3 MHz frequency offset was measured with a center frequency of 1.617 GHz

Hierarchical performance estimation of analog blocks using pareto fronts

Deniz, Engin (Dogus Author) -- Conference full title: 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010; Berlin; Germany; 18 July 2010 through 21 July 2010This paper presents a general approach for hierarchical performance estimation (PE) of any analog system. Not only PE is evaluated by the extracted Pareto Fronts (PF) but also an approximate design of the system is obtained. PE of an analog system requires a well-determined performance design space (PDS) exploration for a given technology. PF which is a very useful technique for evaluating the performance space, provides the set of all optimal trade-offs of competing performances of a given block. Thus, the designer can easily get insight into the capability of the system. In this work, a three-level system is divided into its subsystems and PF of each subsystem is determined. Then, hierarchical methodology of PF composition is applied from lower levels to higher levels so the PF of the main system is obtained with less computational effort. The novelty of the work lies on using simple algorithms instead of complex optimization algorithms and simulation loops

A Sigma-Delta ADC design automation tool with embedded performance estimator

A system-level design automation tool for designing discrete time, switched-capacitor, Sigma Delta analog-to-digital converters is presented. The presented work utilizes a performance estimator based on EKV models. The design automation tool takes advantage of high level analytical single-bit and multibit models of the building blocks. With the contribution of the performance estimator module, the tool provides an extensive design environment for designing Sigma-Delta analog-to-digital converters. Developed models and their effects are presented with examples. Design examples for 0.5 and 0.35 mu m technologies are provided for proving the flexibility of the design automation tool

Weight Quantization for Multi-Layer Perceptrons using Soft-Weight Sharing

We propose a novel approach for quantizing the weights of a multi-layer perceptron for ecient VLSI implementation. Our approach uses soft-weight sharing, previously proposed for improved generalization and considers the weights not as constant numbers but as random variables drawn from a Gaussian mixture distribution; which includes as its special cases k-means clustering and uniform quantization. This approach couples the training of weights for reduced error with their quantization. Simulations on synthetic and real regression and classi- cation data sets compare various quantization schemes and demonstrate the advantage of the coupled training of distribution parameters.

A comparative evaluation of edge detectors and improvement of edge detection via preprocessing in the presence of noise

Dans cette étude, les performances de différents algorithmes pour la détection de côtés sous la présence du bruit sont comparées, en plus préprocès et les méthodes pour la réduction du bruit basées sur la performance de la détection de côtés sont aussi évaluées. Il est évident d'utiliser les algorithmes de préprocès qui tendent à préserver l'information de côtés en réduisant le bruit afin d'améliorer la performance du détecteur des côtés